Parallel architecture is required for high throughput turbodecoder to meet the data rate requirements of the emerging wireless communicationsystems. However, due to the severe memory conflict problemcaused by parallel architectures, the interleaver design has become amajor challenge that limits the achievable throughput. Moreover, the highcomplexity of the interleaver algorithm makes the parallel interleavingaddress generation hardware very difficult to implement. In this paper,we propose a parallel interleaver architecture that can generate multipleinterleaving addresses on-the-fly. We devised a novel scheduling schemewith which we can use more efficient buffer structures to eliminate memorycontention. The synthesis results show that the proposed architecturewith the new scheduling scheme can significantly reduce memory usageand hardware complexity. The proposed architecture also shows greatflexibility and scalability compared to prior work.
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